Nmos dynamic content-addressable-memory cam cell with self-booting pass

Abstract

A content-addressable memory (CAM) cell isolates the gate nodes of pass transistors during a write operation. Select transistors between the word line and the pass-transistor gates are driven high by a column-select signal. The bit lines are precharged low. The word line is driven high to Vcc, and the select transistors drive the pass-transistor gates to Vcc-Vtn. One of the bit lines is then driven high to Vcc while the other bit line is held low. As the bit line swings high, capacitive coupling drives one of the pass-transistor gate nodes higher, above Vcc-Vtn. The select transistor then isolates the gate node from the word line. As the bit line continues to swing high, more coupling drives the gate node above Vcc. The boosted gate-node voltage increases the current drive of the pass transistor, accelerating the write operation. When the word line drop to ground, the select transistors drain the gate nodes, disabling the pass transistors and dynamically storing charge on the gates of storage transistors. The drains of the storage transistors are connected to a match line through a pair of match transistors. The gates of the match transistors are connected to the bit lines. The match transistors and storage transistors form an exclusive-OR (XOR) function with two series connections to the match line. When both a match transistor and a storage transistor in series are on, the match line is discharged, indicating a mis-match.