Data transfer method between buses, bridge devices for interconnecting

Abstract

The object of the present invention is to eliminate, in a data processing system having multiple buses, a combination of devices that can not be accessed via a PCI to PCI bridge. When an access request is issued to an S.sub.-- ISA device by an S.sub.-- PCI device, a PCI to PCI bridge determines whether or not a requested address is outside a blocked area, and whether or not the address matches an address stored in a retry register. When the requested address does not match the address in the retry register, the PCI to PCI bridge mistakes the access request for an access to a P.sub.-- PCI device. Thus, the PCI to PCI bridge positively decodes the access request on the S.sub.-- PCI bus, and transmits an access request on the P.sub.-- PCI bus. However, since none of the P.sub.-- PCI devices do not decode the request, the PCI to PCI bridge has to terminate the bus cycle on the P.sub.-- PCI bus by master abort. At this time, the PCI to PCI bridge stores the requested address in the retry register, and terminates the bus cycle on the S.sub.-- PCI bus in the retry manner. Following this, although the S.sub.-- PCI device tries again to access the S.sub.-- ISA device, the PCI to PCI bridge refers to the address in the retry register and does not decode the access request. Since none of devices on the S.sub.-- PCI bus positively decodes the access request, the PCI to ISA bridge subtractively decodes the request. As a result, the access request is transmitted to the S.sub.-- ISA bus, and the S.sub.-- ISA device can decode this request, thereby establishing a correct bus cycle.