The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 13, 2000
Filed:
Apr. 08, 1999
Kazunari Inoue, Hyogo, JP;
Hideaki Abe, Hyogo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A DRAM includes a data transfer pipeline register group between a dynamic memory cell array and a static memory cell array, a first unidirectional read bus and a first unidirectional write bus connected between a data transfer bus group and the data transfer pipeline register group, and a second unidirectional write bus and a second unidirectional read bus connected between the data transfer pipeline register group and the static memory cell array. The operating frequency of the second unidirectional write bus and the second unidirectional read bus is N times the operating frequency of the first unidirectional read bus and the first unidirectional write bus. The number of lines of the second unidirectional write bus and the second unidirectional read bus is 1/N time the number of lines of the first unidirectional read bus and the first unidirectional write bus. The dynamic memory cell array is further divided into a hierarchical manner of main banks and subbanks.