The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 13, 2000
Filed:
Dec. 23, 1998
Byeng-Sun Choi, Kyunggi-do, KR;
Young-Ho Lim, Kyunggi-do, KR;
Abstract
A word line voltage generating apparatus is provided for a multi-level memory device including a plurality of memory cells, each of which has a programmable threshold voltage such that the memory cell produces a current in response to a word line voltage applied thereto. The apparatus includes a plurality of memory cell referenced regulators connected to an output terminal that is configured to connect to the plurality of memory cells, a respective one of the memory cell referenced regulators including a variable current mirror having a controlled current path and an output current path including the output terminal, the controlled current path having a controlled impedance therein that provides a variable impedance responsive to a control voltage applied thereto such that current produced at the output terminal is proportional to current in the controlled current path, and a control circuit connected between the output terminal and the controlled impedance and including a dummy memory cell having a predetermined threshold voltage, the control circuit operative to apply a control voltage to the controlled impedance to vary a current at the output terminal when an output voltage at the output terminal is greater than a sum of the predetermined threshold voltage of the dummy memory cell and a predetermined offset voltage. According to an embodiment of the present invention, the control circuit comprises a dummy memory cell transistor connected in series with a resistor.