Operation speed measuring circuit and semiconductor device incorporating

Abstract

An operation speed measuring circuit measures a difference in propagation delay time between first and second path 2, 3 including logic gates connected in series and thus confirms that an element provided on a chip obtains a specified operation speed. This operation speed measuring circuit is so constructed as to be controllable by an input signal IN from one input terminal 1 and can be therefore disposed in such an area that the number of placeable terminals is restricted down to a small number. When this operation speed measuring circuit is provided with a power supply terminal independent of other circuits, constructions of other circuits can be independently designed. When the operation speed measuring circuit is disposed in the area independent of an intra-chip integrated circuit design area, a degree of freedom of designing other circuits is improved. This independent area is set in one of corner areas on the semiconductor chip that have hitherto been nothing but empty areas, the degree of freedom of designing the circuit is further improved.