Memory controller and method for intermittently activating and idling a

Abstract

A memory controller and method for intermittently providing a clock signal to a synchronous memory. While no transactions are occurring, a clock signal is held in an idle state. Upon the start of a transaction with the synchronous memory, the clock signal is activated. When activated, the clock signal functions as a periodic timing reference clock. The clock signal remains active during the transaction. Upon completion of the transaction, the clock signal returns to the idle state. In one embodiment, a finite state machine utilizes a counter to control the process. Upon the start of a transaction with the synchronous memory a new count is loaded in a counter. The value for the new count depends, for example, on the number of commands necessary to complete the transaction. The counter, beginning with the new count, regularly increments. When the counter reaches a maximum value, the clock signal returns to the idle state. The clock signal remains in the idle state until the start of a second transaction with the synchronous memory. Then, again the clock signal is activated. The clock signal remains active during the second transaction. Upon completion of the second transaction, the clock signal is again returned to the idle state.