The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2000

Filed:

Jan. 27, 1998
Applicant:
Inventors:

Carl John Knudsen, Gilbert, AZ (US);

Ken Jaramillo, Phoenix, AZ (US);

Assignee:

VLSI Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; H05K / ; H01L / ;
U.S. Cl.
CPC ...
710129 ; 710126 ; 710100 ;
Abstract

A system is delineated comprising, in combination, an integrated circuit having N internal masters coupled to a buried, internal bus, and register circuitry coupled to the buried, internal bus and having an output providing status data for each of the N internal masters. The output from the register circuitry is directly coupled to a processor for permitting the processor to monitor request and grant status for each internal master, thereby allowing the processor to keep track of which, if any, of the internal masters attempt to 'hog' the internal, buried bus. Additionally, the processor can set enabling registers located in the register circuitry to one value for permitting properly operating internal masters to have access to the internal, buried bus, and to another value to disable one or more 'hogging' internal masters from accessing the internal, buried bus. The system further includes N external devices coupled, on a one-to-one basis, to the N internal masters.


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