Transaction based windowing methodology for pre-silicon verification

Abstract

A system and method for detecting timing-related functional problems in an HDL design of a computer system component are disclosed. A simulated model of the HDL design is supplied with a reference signal through a simulated bus. A bus transaction signal is then applied to the simulated model through the same or different simulated bus. The delay between the bus transaction signal and the reference signal is then varied over a range of values, and the simulated model's response to the bus transaction signal for each such delay value is received and analyzed by a transaction checker stored in the computer system memory. The duration of the bus transaction signal may also be varied. This methodology allows conversion of system waveform relationships, which could be observed on a physical system incorporating a manufactured version of the computer system component under test, into simulation waveforms with the same relative relationship. Problems that were once found only after the device was manufactured can now be detected prior to the manufacturing stage.