Read only memory having bias circuits

Abstract

The disclosure is a read only memory having a memory cell array formed of a plurality of memory cells coupled to wordlines and bitlines, the bitlines being alternately connected to main bitlines and ground lines. The invented read only memory include an address transition detection signal source. It also includes a first delay circuit for receiving the address transition detection signal and for generating a first discharge signal for driving the ground lines. It also includes a second delay circuit for receiving the address transition detection signal and for generating a second discharge signal for driving the main bitlines. It also includes a first pulse circuit for receiving the first discharge signal and for generating a first precharge signal for driving the ground lines. Finally, it includes a second pulse circuit for receiving the second discharge signal and for generating a second precharge signal for driving the main bitlines. The timing of the delay and pulse circuits are such that the trailing edges of the first and second discharge signals are substantially simultaneous with one another and that the leading edges of the first and second precharge signals are substantially simultaneous with one another. The result is that the voltage levels on a selected main bitlines and a non-selected ground line are substantially identical, permitting the memory to be read reliably.