Digital phase locked loop circuit for pcr recovery

Abstract

Disclosed is a DPLL circuit including a PCR register receiving and storing PCR values; an LPCR counter counted by a system clock; an LPCR register fetching an LPCR value every PCR input cycle; a phase error detector determining a difference in values stored in the PCR and LPCR registers, and calculating a present phase error requiring compensation; an interpolator interpolating signals between phase error values; a gain calculator determining a difference between consecutive LPCR values, then calculating a gain value, a D/A converting portion multiplying values output from the interpolator and the gain calculator, then converting the resulting signals into analog signals; and a VCO generating system clock frequencies according to signal voltage output from the D/A converting portion. In another aspect, the DPLL circuit is used in MPEG2 systems. Here, the PCR register receives and stores PCR values, and the LPCR register fetches LPCR values, the PCR and LPCR values including a 9-bit extension and a 33-bit base, the base increasing by 1 every time the extension becomes 300. Further, the VCO generates frequencies in a predetermined range from 27 MHz according to signal voltage output from the D/A converting portion, and an STC circuit adds the difference in values between the PCR and the LPCR values to the LPCR base value, then outputs the resulting value.