The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2000
Filed:
Dec. 29, 1997
Shahram Ghahremani, Escondido, CA (US);
Metaflow Technologies, Inc., La Jolla, CA (US);
Abstract
The present invention provides a level sensitive circuit connected to the output portion of a register, which synchronizes an asynchronous input to a clocked network driven by the CPU system clock. The level sensitive circuit ensures that the output of the synchronizing register will always be a definite binary signal, i.e. logical 0 (ground, or absence of voltage) or logical 1 (voltage). The present invention not only minimizes the occurrence of a metastable condition, but also recognizes that metastability may occur. The present invention is optimized to prevent metastability and includes a synchronizing latch having an output circuit with a feedback mechanism that effectively causes the output voltage of the register to be a valid signal only when any metastable condition has resolved itself. More particularly, the non-inverted output of the register is utilized as feedback to the level sensitive circuit. Based on the various threshold voltages of the transistors in the level sensitive circuit, the output of the register will switch only when a sufficiently stable voltage (high or low) is present as the output of the level sensitive circuit.