The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2000

Filed:

Jul. 14, 1997
Applicant:
Inventor:

Chika Nakajima, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438291 ; 438302 ;
Abstract

There is provided a method of fabricating a lateral MOS transistor, including the steps of (a) forming a gate oxide film on a semiconductor substrate, (b) forming a gate electrode on the gate oxide film, (c) forming a mask covering one of regions of the semiconductor substrate adjacent to the gate electrode, (d) ion-implanting the semiconductor substrate with impurities having a first electrical conductivity as the semiconductor substrate is being rotated around the gate electrode, at an angle relative to the semiconductor substrate to form a channel region in an uncovered region, (e) ion-implanting the semiconductor substrate with impurities having a second electrical conductivity around the gate electrode in self-aligned manner to thereby form source and drain regions. It is preferable that ion-implantation in the step (d) is carried out in the desired number of times. The above mentioned method makes it possible to form a channel region having a steep impurities-concentration profile just below the gate electrode, ensuring that performances of MOS transistor are improved, and that other MOS transistors can be formed on the same semiconductor substrate.


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