Memory device with a memory cell array in triple well, and related

Abstract

A memory device comprising a semiconductor material substrate with a dopant of a first type; a first semiconductor material well with a dopant of a second type formed in the substrate; a second semiconductor material well with a dopant of the first type formed in said first well; an array of memory cells formed within said second well. Each memory cell comprises a first electrode and a second electrode respectively formed by a first and a second doped regions with dopant of the second type formed in said second well, and a control gate electrode. The memory array comprises a first plurality of strips of conductive material extending over said second well in a first direction and forming rows of memory cells, a second plurality of strips of conductive material extending over said second well in a second direction substantially orthogonal to said first direction and forming columns of memory cells, each strip of said second plurality electrically contacting the first electrodes of a respective group of memory cells, a third plurality of strips of conductive material extending over said second well in said second direction and intercalated to the strips of the second plurality, electrically contacting the second electrodes of the cells. A fourth plurality of strips of conductive material is provided extending over said second well in said second direction and intercalated to the strips of said second and third pluralities, electrically contacting the second well in a succession of contact points distributed longitudinally to each strip of said fourth plurality.