The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2000
Filed:
Sep. 17, 1998
Kiran B Buch, Fremont, CA (US);
Mehul R Vashi, Santa Clara, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method is provided for scan testing that eliminates the need for balancing internal scan clock delays. According to the method of the invention, multiple scan clocks are provided, each being provided to a different set of flip-flops. The skew between the active edges of the scan clocks is deliberately increased to the point where each set of flip-flops has plenty of time to settle before the next set of flip-flops receives a clock pulse. Because scan testing is typically performed at clock speeds of only about 1 Megahertz, there is time for each of the scan clocks to pulse separately from all the others, without increasing the test time. The increased delay between scan clock pulses eliminates the need for balancing internal delays on the scan clock paths, thereby greatly reducing the number of placement and routing iterations required to achieve a functional design.