The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2000
Filed:
Jul. 07, 1998
Steven M Labram, Crolles, FR;
U.S. Philips Corporation, New York, NY (US);
Abstract
An output stage comprising an input terminal (IP) for receiving an input signal (V.sub.i); an output terminal (OP) for delivering an output signal (V.sub.o) in response to the input signal (V.sub.i); a first (1) and second (2) supply terminal for receiving a supply voltage (SV); a field effect transistor (Q1) comprising a gate (GN), and a main current path between a source and a drain coupled between the first supply terminal (1) and the output terminal (OP); and slewing control means (SCM) for reducing the speed of voltage change at the gate (GN) of the field effect transistor (Q1) for reducing the speed of current change through the main current path of the field effect transistor (Q1) when the output signal (V.sub.o) changes from a first steady state (FST) via a transition area (TRE) to a second steady state (SST). The slewing control means (SCM) comprises first means for reducing the gate-source voltage V(GN) between the gate (GN) and the source of the field effect transistor (Q1) in at least part of the transition area (TRE) when the field effect transistor (Q1) changes from a nonconducting state to a conducting state and thus causing the output signal (V.sub.o) to be changed from the first steady state (FST), via the transition area (TRE), to the second steady state (SST). The first means avoid the field effect transistor (Q1) to become out of saturation, and thus avoids an abrupt change of the current through the field effect transistor (Q1), thereby avoiding relatively large voltage spikes at the first supply voltage (SV) and/or the output signal (V.sub.o).