Sample-and-hold circuit having reduced subthreshold conduction effects

Abstract

An integrated sample-and-hold S/H circuit includes a subthreshold conduction current compensation circuit for reducing undesired effects of subthreshold conduction current in a first field-effect transistor (FET) during the holding time. More particularly, the S/H circuit may include a substrate, a sampling capacitor formed on the substrate, and the first FET. The first FET has a first conduction terminal for receiving the input signal, a second conduction terminal connected to the sampling capacitor, and a control terminal. The control terminal is responsive to control signals for connecting the input signal to the sampling capacitor during a sampling time and for disconnecting the input signal from the sampling capacitor during a holding time. The first FET preferably further includes a body which unfortunately creates a parasitic diode connected to the sampling capacitor. A unity gain buffer amplifier may be connected to the body of the first FET during the holding time for applying a holding voltage from the sampling capacitor to the body to thereby reduce undesired effects from the parasitic diode. The subthreshold current conduction compensation circuit causes a voltage at the first conduction terminal of the first FET to be substantially equal to a voltage at the second conduction terminal of the first FET during the holding time. This may be accomplished by coupling the holding voltage from the output of the buffer amplifier to the node between two series connected FETs.