The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2000
Filed:
Dec. 02, 1997
Emil S Ochotta, Campbell, CA (US);
Douglas P Wieland, Sunnyvale, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A direct connect mesh routing structure is provided for interconnecting configurable logic blocks within a programmable logic device. The structure includes multi-bit interconnect busses and a highly regular structure distributed throughout a configurable array enabling high direct interconnect utilization to adjacent and non-adjacent logic blocks, high speed circuit implementation, and improved timing characteristics. The direct connections of the invention are the preferred interconnect path between logic blocks because they substantially reduce the average interconnect delay, thereby allowing the programmable logic device to operate at a higher speed.