Method and apparatus for a low power self test of a memory subsystem

Abstract

A technique self tests a memory system having memory modules that operate at a normal operating clock rate during a normal operating mode. Each memory module has multiple arrays of synchronous dynamic random access memory devices. The technique involves obtaining, independently of a central controller, time phase identifiers that respectively correspond to the memory modules, and reducing the normal operating clock rate to a reduced clock rate. The technique further involves executing, in the memory modules, self test transactions in different time phases depending on the obtained time phase identifiers. The memory modules initiate execution of self test transactions at the reduced clock rate. Multiple memory modules execute self test transactions in each of the different time phases. Each memory module executes self test transactions that alternately access the multiple arrays of that memory module. Preferably, the time phase identifiers are based on module identifiers that uniquely identify the memory modules.