Clock-synchronized memory device and the scheduler thereof

Abstract

The present invention provides inside a scheduler a shift register, which performs a shift operation in synch with an external clock, or a clock generated thereby. Then, for example, when controlling latency from the supply of a command until the start of a column operation, at the time the command is supplied, a column access signal is stored in a shift register location, which corresponds to its latency. Because the shift register performs a shift operation in synch with a clock, a column access signal is outputted subsequent to a number of clock pulses, which correspond to its latency. A column control circuit, in response to the timing at which this column access signal is outputted, acquires a column address and other data required for a column circuitry operation, and starts a column circuitry operation. A configuration such as this simplifies the operation of the scheduler. In the above-described shift register, setting an internal operation command signal, which starts a prescribed internal operation, makes it possible to readily manage latency up until the start of an arbitrary internal operation.