The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 2000
Filed:
Jan. 16, 1998
Keiichi Ito, Saitama, JP;
Fuji Xerox Co., Ltd., Tokyo, JP;
Abstract
An input/output controller apparatus has a CPU arranged for directing an FPGA to generate a desired trace logic circuit and a channel controller to start communication with a host system. The channel controller while performing the communication with the host system delivers a channel sequence number via a buffer to the FPGA. In response, the FPGA saves the channel interface signal and the channel sequence number at given timing. When an error occurs during the communication, the CPU identifies the cause of the error by reviewing the channel interface signal and the channel sequence number saved in the FPGA. If the cause of the error fails to be identified, the FPGA is directed to generate another trace logic circuit suited for identifying the cause of the error. Accordingly, the size of a data storage used for tracing will be minimized and the overall area for installation of the apparatus will be minimized comparatively as well as the duration required for examining the communication between the host system and its peripherals will be reduced considerably. The apparatus may be linked to a plurality of host systems for equal advantages.