The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 2000
Filed:
May. 05, 1998
Applicant:
Inventors:
Masayuki Yamashita, Hyogo, JP;
Hideki Kawamura, Hyogo, JP;
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518904 ; 36518908 ;
Abstract
A bit line load element for reducing a bit line amplitude during data reading is formed of p- and n-channel MOS transistors connected in parallel. When a word line is driven to the selected state, the p-channel MOS transistor is held off. In the data write operation, both the n- and p-channel MOS transistors are turned off. Even under a low power supply voltage, a sufficiently large bit line amplitude can be produced without an influence by a size of the bit line load element. By deactivating the bit line load element in the data write operation, it is possible to prevent generation of a DC current during data writing.