The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 2000
Filed:
Sep. 10, 1998
Ping Xu, Milpitas, CA (US);
Seiko Epson Corporation, Tokyo, JP;
Abstract
An analog buffer comprising a bias circuit, an n input stage, a p-input stage, and a push-pull output stage which generates an output voltage signal and which is configured and operated such that the output voltage signal is able to quickly and accurately respond to changes in the input voltage signal. The push-pull output stage comprises a pair of output transistors which having a common drain connection forming an output node where the output voltage signal is generated. The push-pull output stage further comprises a first group of PMOS transistors, one of which is responsive to a first control signal generated in the n-input stage to increase the output signal in response to an increase in the input signal, and a second group of NMOS transistors, one of which is responsive to a second control signal generated in the p-input stage to decrease the output signal in response to a decrease in the input signal. A third group of MOS transistors assists in increasing the output signal in response to an increase in the input signal at a relatively high end of the input signal range, and a fourth group of MOS transistors assists in decreasing the output signal in response to a decrease in the input signal at a relatively low end of the input signal range.