The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 2000
Filed:
Jan. 21, 1998
Naoki Nagashima, Kanagawa, JP;
Sony Corporation, Tokyo, JP;
Abstract
A manufacturing method of a complementary MOS transistor capable of providing line width stability at the time of lithography of gate patterning and suppressing punch through of an impurity from the silicon gate electrode to the side of a substrate is proposed. A method for manufacturing a semiconductor device having a complementary MOS transistor includes the steps of forming a poly-crystalline semiconductor film (6) serving as a gate electrode on one major surface of a semiconductor substrate (3), (4) via a gate insulation film (5), forming a first solid phase diffusion source (7) containing an impurity of a first conduction type selectively on a portion of the poly-crystalline semiconductor film (6) corresponding to a first channel MOS transistor forming region (4), forming a second solid phase diffusion source (9) containing impurities of a second conduction type on an entire surface including a surface of the first solid phase diffusion source (7) and a surface of the poly-crystalline semiconductor film (6) corresponding to a second channel MOS transistor forming region (3), polishing the second solid phase diffusion source (9) by a chemical mechanical polishing technique to a position where the first solid phase diffusion source (7) is exposed, and patterning the poly-crystalline semiconductor film (6) together with the first solid phase diffusion source (7) and the second solid phase diffusion source (9) to attain a gate electrode pattern.