The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 16, 2000
Filed:
Mar. 30, 1998
Owen S Bair, Saratoga, CA (US);
Saravana Soundararajan, Sunnyvale, CA (US);
Adam Kablanian, San Jose, CA (US);
Thomas P Anderson, Sunnyvale, CA (US);
Chuong T Le, San Jose, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method provides an on-chip repair technique to fix defective row or I/O memory lines in an ASIC memory array with redundancy row or I/O memory lines. The method employs progressive urgency and dynamic repair schemes to optimize the allotted time for repairing defective row and I/O memory lines. Progressive urgency scheme increases the need to repair relative to the available redundancy row or I/O memory lines over the entire repairing time. Dynamic repair executes a mandatory-row or a mandatory-I/O repair as defective row or I/O memory lines are detected. In addition, a recurrence error reroutes the address location of a redundancy memory line to another address location of another redundancy memory line in the event that such redundancy memory line itself is defective, and thus requires further repair.