The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 16, 2000
Filed:
Dec. 28, 1998
Hi-Choon Lee, Kyunggi-do, KR;
Seung-Cheol Oh, Kyunggi-do, KR;
Samsung Electronics Co., Ltd., Suwon, KR;
Abstract
A synchronous memory includes a column main-decoder circuit that is directly coupled to column select lines (CSL), and a timing controller that controls both enable timing and disable timing of the column select lines by controlling the column pre-decoder. The CSL timing controller generates a CSL timing control signal representative of the enable timing and the disable timing of the column select lines. The column pre-decoder is either enabled or disabled depending upon logic states of the CSL timing control signal. The timing controller includes a first control circuit which provides a CSL enable control signal, a CSL disable control circuit which provides a CSL disable control signal, and a flip-flop circuit which receives the CSL enable and disable control signals and provides the CSL timing control signal.