Semiconductor memory device with true/complement redundancy scheme

Abstract

Disclosed is a semiconductor memory device including a redundancy controller. The redundancy controller is structured using pass gate logic, dynamic inverter circuits, and a true/complement decoder scheme. The redundancy controller includes first and second redundancy enable circuits corresponding respectively to first and second redundant columns. A first and second fuse boxes are coupled respectively to the first and second redundancy enable circuits. The first and second fuse boxes each include a fuse box circuit corresponding to the column address signals and a fuse element. Each fuse box circuit receives a corresponding pair of true and complement column address signals and manipulates the true and complement column address signals responsive to the fuse element. A first decoding means decodes the manipulated versions of the true and complement column address signals and generates first and second true decoded pulse signals and first and second complement decoded pulse signals. A second decoding means decodes the manipulated versions of the true and complement column address signals and generates third and fourth true decoded pulse signals and third and fourth complement decoded pulse signals. A sense amplification control signal generating means produces the sense amplification control signal responsive to the first, second, third, and fourth true decoded pulse signals and the first, second, third, and fourth complement decoded pulse signals. A row select signal generating means produces the row select signal responsive to first, second, third, and fourth true decoded pulse signals. The above-described redundancy controller improves the redundancy speed.