The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2000

Filed:

Mar. 24, 1999
Applicant:
Inventors:

Andrea Ghilardelli, Cinisello Balsamo, IT;

Carla Maria Golla, Sesto San Giovanni, IT;

Matteo Zammattio, Milan, IT;

Stefano Zanardi, Seriate, IT;

Assignee:

STMicroelectronics, S.r.l., Agrate Brianza, IT;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518533 ; 365154 ;
Abstract

A switching circuit comprising a supply voltage, a reference voltage, a line suitable to carry a negative voltage, an input for a control signal, suitable to supply to a first output node and to a second output node two voltages respectively equal to supply voltage and to line voltage or, alternatively, to line voltage and to supply voltage, in response to the control signal. There are first interrupting means, second interrupting means, third interrupting means, fourth interrupting means, the first and third interrupting means connected in series between the supply voltage and the line, the second and fourth interrupting means connected in series with each other and in parallel to first and third interrupting means, the first output node corresponding to common node between the first interrupting means and the third interrupting means, the second output node corresponding to common node between the second interrupting means and the fourth interrupting means, the control signal controlling first interrupting means and second interrupting means in such a way that when the first interrupting means are open, also the fourth interrupting means are open whereas the second interrupting means and third interrupting means are closed, connecting the first output node to line and the second output node to supply voltage, and vice versa when the first interrupting means are closed, also fourth interrupting means are closed whereas the second interrupting means and third interrupting means are open, connecting the first output node to supply voltage and the second output node to line.


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