The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 16, 2000
Filed:
Apr. 20, 1998
Mark V Faulkner, Boulder Creek, CA (US);
Malkiat S Nijjar, San Jose, CA (US);
Clifford A Mohwinkel, San Jose, CA (US);
Endgate Corporation, Sunnyvale, CA (US);
Abstract
First and second spaced-apart planar circuit ground conductors are formed on a base substrate. Multiple stages of an amplifier each have a field effect transistor (FET) flip mounted onto the substrate. A signal-return line couples the sources of the FETs together and functions as a radio frequency (RF) grounds for the amplifier. Direct-current-blocking coplanar couplers couple the amplifier input and output to external circuits. A single voltage supply applies a bias voltage to the drains of the FETs. A source resistance device couples each source terminal to circuit ground. The source resistance devices may be formed of two series-connected resistors. The gate of each FET is coupled to one of the circuit ground conductors through one of the source resistors. The other source resistor thereby provides a gate-to-source voltage for biasing the FET. Alternative embodiments provide a community bias circuit in which signal-return lines of transistors conducting different signals are interconnected and coupled to the bias circuit ground.