Method for manufacturing a native mos p-channel transistor with a

Abstract

A method is provided of manufacturing a P-channel native MOS transistor in a circuit integrated on a semiconductor which also includes a matrix of non-volatile memory cells of the floating gate type with two polysilicon levels having an interpoly dielectric layer sandwiched between the two polysilicon levels. The method has the following steps: (1) masking and defining active areas of the discrete integrated devices; (2) masking and defining the first polysilicon level using a Poly1 mask; and (3) masking and defining an intermediate dielectric layer using a matrix mask. The length of the native threshold channel of the native transistor is defined by means of the matrix mask and by etching away the interpoly dielectric layer. A subsequent step of masking and defining the second polysilicon level provides for the use of a Poly2 mask which extends the active area of the transistor with a greater width than the previous mask in order to enable, by subsequent etching, the two polysilicon levels to overlap in self-alignment over the channel region.