Hidden precharge pseudo cache dram

Abstract

A new DRAM architecture, HPPC DRAM, is provided to support a high performance and low cost memory system. The HPPC DRAM has integrated the following concepts into a single DRAM chip. First, superset pin definitions backward-compatible to the traditional fast-page-mode DRAM SIMM. This allows one memory controller to support a memory system having both a traditional fast-page-mode DRAM and HPPC DRAM of this invention. Secondly, combining a memory array, a register of 4:1 Mux/Demux function, a RAS buffer/decoder, a CAS buffer/decoder, a burst address counter, a page register/comparator, a sequencer and a data buffer into a single DRAM IC chip. Using these intelligent peripheral circuits, the HPPC DRAM execute a pipeline cycle request and precharge cycle stealing. Thirdly, a precharge cycle stealing pipeline is implemented to the timing chain of read operation to eliminate the precharge cycle time which is achieved by executing read drive concurrently to the precharge cycle. This read timing chain shows that a zero wait state is sustained if there is a page-hit. Fourthly, a precharge cycle stealing pipeline is implemented to the timing chain of write operation to eliminate the precharge cycle time which is achieved by executing precharge cycle concurrently to address predecoding and data strobing.