Diode modulator generating a line s-correction

Abstract

A diode modulator circuit which is adapted to supply an acceptable S-correction of the S-linearity error of the line scanning of a picture tube (CRT) at substantially different line scan widths. A known diode modulator has two loops. The first loop includes a series arrangement of a line deflection coil (LD) and an S-capacitor (CS), which series arrangement is arranged in parallel with a first flyback capacitor (CF1) and a first diode (D1). The second loop includes a modulator coil (LB) arranged in parallel with a second flyback capacitor (CF2) and a second diode (D2). The two loops are arranged in series. An inner-pincushion capacitor (CSM) is arranged in a common path in which the line deflection current (Id) and a modulator current (Ib) flowing through the modulator coil (LB) flow in opposite directions. The amount of S-correction depends on the values of the S-correction capacitor (SC) and the inner-pincushion capacitor (CSM). The S-capacitor (CS) has been omitted in the subject diode modulator. In this way, the amount of S-correction at minimal scan width will be zero because the common current (Im) flowing in the common path is zero if the diode modulator is in equilibrium. The diode modulator according to the invention can thus cope with picture tubes (CRT) which require a very low amount of S-correction at a small scan width without the need for an additional capacitor (CS2) and a thyristor switching circuit (T) to activate the additional capacitor (CS2) to lower the amount of S-correction at the small scan width.