The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 2000
Filed:
Jan. 06, 1998
Chihiro Tadokoro, Tokyo, JP;
Junichi Yamashita, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
An n.sup.- layer (2E) having a low impurity concentration is epitaxially grown on a surface (S1) of an n.sup.+ silicon substrate (1) having a high impurity concentration to a depth (D), and phosphorus ions (P) are implanted from the surface (S1) to the inside of the n.sup.- layer (2E). A SiO.sub.2 film is formed on the surface S1 by thermal oxidation, and an opening hole is formed in the SiO.sub.2 film. Using the opening hole, p-type impurities are implanted and diffused by thermal oxidation in the ion-implanted n.sup.- layer (2E), forming a p-type diffusion layer (well) from the surface (S1) to a predetermined depth. In this way, an n layer is formed in place of the n.sup.- layer (2E). The concentration distribution of impurity in the n layer monotonically decreases from the side of the surface (S1) and reaches its minimum on the side of an interface (BS). Then, a predetermined electrode is formed, completing the device. Thus, variations in both on-state resistance and breakdown voltage are reduced in a semiconductor device having a pn junction.