The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2000

Filed:

Oct. 19, 1998
Applicant:
Inventor:

William W Lee, Palo Alto, CA (US);

Assignee:

Other;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438257 ; 438266 ;
Abstract

A compact, low current flash EPROM cell that is scaleable to dee-submicron levels for future generations of flash memory arrays is disclosed. This flash memory cell can be fabricated using a twelve masks, triple-poly, salicided process. Source-side injection for programming and poly-to-poly erasing demand very little current and power and such demand can easily be met by charge pump techniques. A select gate in series with the cell channel guarantees enhancement threshold and its sell-alignment and constant channel length will give uniform electrical characteristics in every respect. A virtual ground array fabricated using a self-aligned salicidation process provides a compact cell with high access speed. The cell area is approximately 3F.times.2F where F is a given minimum dimension.


Find Patent Forward Citations

Lee, William. (2000). Method of fabricating virtual ground ssi flash eprom cell and array (U.S. Patent No. 6060356). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6060356

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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