The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 2000
Filed:
Dec. 15, 1997
Nicholas F Pasch, Pacifica, CA (US);
Joe W Zhao, San Jose, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
Described is an improvement in a process wherein integrated circuit structures are formed on a front surface of a silicon substrate and at least one layer of copper is deposited on the front surface of the substrate to form a layer of copper interconnects, and wherein at least some copper is also deposited on the back surface of the substrate during this deposition. The improvement comprises: prior to the end of the formation of the integrated circuit structures, abrasively removing, from the backside of the substrate, copper deposited thereon during the deposition of copper on the front surface. The step of abrasively removing copper from the back side of the substrate is preferably carried out before exposure of the substrate and the copper thereon, including copper deposited on the back side of the substrate, to any subsequent high temperature processing, and preferably, the step of abrasively removing the copper from the backside of the substrate comprises a chemical/mechanical polishing step which leaves a polished surface on the backside of the substrate to facilitate subsequent mounting or packaging of the integrated circuit structures.