Multi-bit test circuit in semiconductor memory device and method thereof

Abstract

A multi-bit test circuit detects the fail cells in a memory block accurately even though there exists a short bridge between bit lines or between memory cells. The circuit includes an input buffer for transferring a same test data bit received from a multi-bit input/output pin to selected ones of the memory cells in each block in response to a multi-bit test enable signal, a plurality of sense amplifier drivers connected to the respective memory cells, for amplifying the test data bits to transfer the amplified data bits to the associated memory cells, and reading out the test data bits stored into the associated memory cells, and a comparator for comparing the same data bits stored into the same block to generate a comparison data bit in response to the multi-bit input/output enable signal, and transferring the comparison data to the multi-bit input/output pin.