The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 02, 2000
Filed:
May. 21, 1998
George McNeil Lattimore, Austin, TX (US);
Terry Lee Leasure, Georgetown, TX (US);
Robert Anthony Ross, Jr, Cedar Park, TX (US);
Gus Wai-Yen Yeung, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A memory array is modified by segmenting the total length of a bitline into smaller bitline sections referred to as local bitlines. Included is an additional bitline into the array for every bitline that has been segmented. This new bitline is referred to as the global bitline. After segmentation, the array appears as several smaller sub-arrays; each sub-array has fewer cells per segmentation (local bitline) than the sum total of cells along the more traditional non-segmented bitline approach. These smaller sub-arrays (local bitline segmentations) are independent of one another and only one sub-array can be accessed per memory request (read/write). The reduced length and cell count per local bitline within each sub-array substantially reduces the total bitline capacitance (e.g., diffusion capacitance) discharged by a single memory cell during a read operation. Reducing bitline capacitance results in faster signal development and restore time on the bitline; thus, several smaller sub-arrays can be cycled much faster than a single large array.