Redundancy scheme providing improvements in redundant circuit access

Abstract

A circuit comprising a main memory array with a block of columns per data I/O, a main read/write block per block of columns, one or more spare memory columns, a bad address detector circuit per spare column, and a read/write block per spare column. A spare column may replace a defective column or cell in any of the blocks of columns. The spare column may be read from/written to via the main read/write block of the column it is replacing, or via its own dedicated read/write block to improve access times. The bad address detector can be configured with programmable elements to produce a control signal when the address of a defective memory element (cell or column) is applied. This signal is then used to disable the defective memory element (and read/write block) and enable a spare column (and read/write block) in its place. The present invention also comprises a recovery circuit on the local data lines (multiplexed to the addressed bitlines). The recovery circuit in the block with the defective column is activated during a spare access. This allows the memory to be tolerant of some of the faults normally combated with column disconnect fuses without the use of such fuses. The present invention also comprises a logic circuit that utilizes a signal synchronized to the address signals to improve the speed of operation of the redundancy scheme.