The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 02, 2000
Filed:
Mar. 09, 1999
Koji Kishimoto, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
There is provided a method of fabricating a semiconductor device, including the steps of forming lower wiring layers on a semiconductor substrate, forming a first silicon oxide film by PECVD, forming a second silicon oxide film containing fluorine by PECVD so that the second silicon oxide film covers the first silicon oxide film and further so that portions thereof formed between the lower wiring layers have a top surface lower than a top surface of portions of the first silicon oxide film located on the lower wiring layers, forming a third silicon oxide film by PECVD so that the third silicon oxide film covers the second silicon oxide film and further so that portions of the third silicon film formed between the lower wiring layers have a top surface higher than a top surface of portions of the first silicon oxide film located on the lower wiring layers, the second silicon oxide film having a greater polishing rate than polishing rates of the first and third silicon oxide films, chemically and mechanically polishing the third and second silicon oxide films until a top surface of portions of the first silicon oxide film located on the lower wiring layers appears, and forming a fourth silicon oxide film by PECVD. The above mentioned method provides an interlayer insulating film having a low dielectric constant and a planarized surface suitable for multi-layer wiring.