Nonvolatile semiconductor memory device

Abstract

After specific data are stored at individual page latches 80.sub.1 to 80.sub.m, the latch data stored at the page laches 80.sub.1 to 80.sub.m are written into one-word memory cells 10.sub.1j to 10.sub.mj. When the data writing is completed, the individual sets of latch data stored at the page latches 80.sub.1 to 80.sub.m are output to bit lines BL.sub.1 to BL.sub.m, to be compared against the memory data stored in the individual memory cells 10.sub.1j to 10.sub.mj. These comparison results are re-stored at the individual page latches 80.sub.1 to 80.sub.m. At this point, if the memory data stored in the memory cells 10.sub.1j to 10.sub.mj have been written correctly, L level data are written at the corresponding page latches 80.sub.i, whereas if they have not been written correctly, H level data are written at the page latches 80.sub.i. The data that have been re-stored at the individual page latches 80.sub.i are output to a data verification line DL to which a verification unit 100 is connected. In other words, the verification unit 100 is capable of performing batch verification for the memory data stored in the one-word memory cells 10.sub.1j to 10.sub.mj. Thus, with the nonvolatile semiconductor memory device according to the present invention, the structure of the circuit for verification ca be simplified and the length of time required for verification can be reduced.