Interconnect structure between heterogeneous core regions in a

Abstract

A programmable interconnect structure is provided whereby core regions of an integrated circuit having circuits of different functional types therein are connected. Ports are defined in a first core region along its boundary with a second core region, and port multiplexers selectively provide signals to the first core region from a variety of conductors in the second core region. In the case where a core region of a first type is placed between two core regions of a second type, a segmented bus structure is provided to preserve connectivity between the two core regions of the second type, while at the same time providing an increased number of independent signals available to the core region of the first type. In the exemplary integrated circuit disclosed herein, a field programmable gate array occupies one core region, and a field programmable memory array occupies another core region.