The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2000

Filed:

Dec. 23, 1996
Applicant:
Inventors:

Bernardo Martinez-Tovar, Albuquerque, NM (US);

John A Montoya, Albuquerque, NM (US);

Assignee:

SCB Technologies Inc., Albuquerque, NM (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257692 ; 257778 ; 257786 ;
Abstract

A semiconductor element, e.g., a semiconductor bridge element (30), is surface mountable as it has thereon a metal layer comprised of metal lands (44) and electrical connectors 45a, 45b and 45c) which terminate in flat electrical contacts (47) on the back surface (35) of the element. Optionally, the element may also contain back-to-back zener diodes (46a, 46b) to provide unbiased protection against electrostatic discharge. When configured as a semiconductor bridge element (30), the element, among other uses, finds use as an igniter (13) for an explosive element. The elements may be made by a method including a cross-cut technique in which grooves (60) cut in the front surface (58) of a silicon wafer substrate (56) intersect grooves (64) cut in the back surface (62) of the wafer. The intersecting grooves (60,64) form a plurality of apertures in the wafer (56), the apertures and grooves helping to define a plurality of dies having side surfaces. A dielectric layer (48) is deposited on the wafer (56) and a polysilicon film (52) is deposited over the dielectric layer (48). A metal layer (44, 45a-45c, and 47) is then deposited on the wafer while it is still intact to provide an electrical connection from the top surface (34) of element (30) along the side surfaces (66a, 66b and 66c, and 68a, 68b and 66c) to the bottom surface (35) to constitute the dies as the semiconductor elements (30). The elements (30) are separated and the electrical contacts (47) of a given element can be mounted directly to a header (36) or the like by soldering, without need for connector wires (14).


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