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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6052518 B1

PDFFull Text
Date of Patent:
Apr. 18, 2000

Filed:

Apr. 30, 1998

Logical circuit automatical design method and system, and computer

Applicant:
Inventors:

Yoshinori Shigeta, Tokyo, JP;

Masatoshi Sekine, Tokyo, JP;

Hiroaki Nishi, Tokoy, JP;

Atsushi Masuda, Tokyo, JP;

Takanao Amatsubo, Tokyo, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:

Foley & Lardner

Primary Examiner:

Paul R Lintz

Assistant Examiner:

Leigh Marie Garbowski

Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
39550019 ;
Abstract

A model of architecture of a processor is called an architecture template. Because a designer selects an architecture template of a special purpose processor which is suitable for an objective signal processing algorithm from an architecture template library, a special purpose processor which is the most suitable for any signal algorithm can be synthesized. Moreover, by providing a method of creating an architecture template simply, even if there is no desirable architecture template, an objective architecture template can be synthesized for a short time.

Find Patent Forward Citations

Shigeta, Yoshinori. (2000). Logical circuit automatical design method and system, and computer (U.S. Patent No. 6052518). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6052518

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