The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2000

Filed:

Jul. 25, 1999
Applicant:
Inventors:

Kevin G Chandler, Loveland, CO (US);

Barry A Alcorn, Fort Collins, CO (US);

Bryan D Boswell, Loveland, CO (US);

John M Heumann, Loveland, CO (US);

Ed O Schlotzhauer, Loveland, CO (US);

Assignee:

Hewlett-Packard Company, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01K / ; G01R / ;
U.S. Cl.
CPC ...
324537 ; 3241581 ; 714734 ;
Abstract

A method for testing node interconnection on a circuit board. The method utilizes an automated test system having at least one test channel, wherein each test channel has a digital driver with a first input and a first output, and a digital receiver with a second output and a second input. The second input of the receiver is coupled to the first output of the driver and to a test probe. The test probe is configured to couple the driver and receiver to one of a plurality of nodes on a circuit board. During a node interconnection test, a first selected node is coupled to a first test channel, and it is determined whether the first selected node is connected to ground. If the first selected node is not connected to ground, a second selected node is connected to ground; a test signal is applied to the first selected node via the digital driver of the first test channel; and it is determined whether the first selected node is connected to the second selected node.


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