The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2000

Filed:

Jul. 16, 1998
Applicant:
Inventors:

Sharad Kapur, Hudson County, NJ (US);

David Esley Long, Morris County, NJ (US);

Jingsong Zhao, Santa Cruz County, CA (US);

Assignee:

Lucent Technologies, Murray Hill, NJ (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
703-5 ; 703 13 ; 342196 ; 367135 ;
Abstract

A layered structure is divided into a plurality of regions. Transmission line equivalents (Green's functions) in the spectral domain are formed between all regions within the layered structure. The spectral domain Greens' function are converted to the spatial domain using a near field and a far field computed for those regions part of a component within the layered structure. The far field is extracted from a compressed database computed from the transmission line equivalents and descriptive of the layered structure. The near field is computed using a prioritization mechanism. Priority is assigned in accordance with the amplitude of a source and the length of the path between regions of interest. Once the physical characteristics of the layers used in the fabrication process of the IC are identified, the database used for computation of the far field is compiled and compressed, and remains unchanged for each new parameter extraction. Thus, compressed, layered Green's functions in the database decouple the computation of the far field from the layer structure and circuit geometry, minimizing computation time.


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