The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 2000
Filed:
Nov. 22, 1996
Peter Chambers, Scottsdale, AZ (US);
Scott Edward Harrow, Scottsdale, AZ (US);
VLSI Technology, Inc., San Jose, CA (US);
Abstract
A method and apparatus for optimizing sample fetching in a peripheral component interconnect (PCI) environment. In one embodiment the present invention generates a first sample page base address corresponding to a first part of a first address received from a digital signal processor (DSP). The present invention also generates a second sample page base address corresponding to a first part of a second address received from the DSP. The first and second generated sample page base addresses are then stored in respective first and second locations within a multiple entry sample page base address cache which can be accessed by the DSP without accessing a PCI bus. The first part of the first address is compared to a first part of a third address. Provided that the first part of the first address and the first part of the third address are the same, the present invention combines a second portion of the third address sent from the DSP with the first generated sample page base address stored in the multiple entry sample page base address cache. The first part of the second address is also compared with the first part of the third address. Provided that the first part of the second address and the first part of the third address are the same, the present invention combines the second portion of the third address sent from the DSP with the second generated sample page base address stored in the multiple entry sample page base address cache. In so doing, the present invention generates a complete address of a sample to be fetched without accessing the PCI bus.