Output buffer including an application-specific sram memory cell for low

Abstract

An application-specific SRAM memory cell includes first and second cross-coupled inverters coupled at first and second nodes for storing a bit of information at the first node and a complement of the bit at the second node, first and second series-connected transistors for coupling a write data signal to the first node in response to a write address signal and a clock having high logical values, third, fourth and fifth series-connected transistors for coupling the second node to ground in response to the write data signal, the write address signal and the clock having high logical values, a sixth transistor for coupling the bit to a read data line in response to a read address signal having a high logical value, a seventh transistor for coupling the complement of the bit to a third node in response to the read address signal having a high logical value, an eighth transistor for coupling the read data line to a power supply terminal in response to the third node having a low logical value, and a ninth transistor for coupling the third node to the power supply terminal in response to the read data line having a low logical value. In memory structures such as register files or arrays, the eighth and ninth transistors provide an output stage that can be shared by each memory cell coupled to the read data line.