Internal power supply generating circuit for a semiconductor memory

Abstract

An internal power supply generating circuit for a semiconductor memory device reduces fluctuations in the external power supply by reducing the rate at which a drive transistor is turned on and off. The circuit includes a drive transistor that generates an internal power signal by reducing the external power supply voltage responsive to a bias signal. A feedback loop generates the bias signal and slows down the rate at which the bias signal changes, thereby reducing the rate at which the drive transistor turns on and off. The feedback loop includes a comparator for comparing the internal power supply voltage to a reference voltage and a bias circuit having a pair of push-pull transistors for generating the bias signal responsive to the output of the comparator. To slow down the rate at which the bias signal changes, the bias circuit includes a resistor coupled in series with the transistors and/or a capacitor couple to the output terminal of the bias circuit. Alternatively, the bias circuit includes a third transistor coupled in series with the push-pull transistors. A voltage divider is coupled to the gate of the third transistor and the gate of one of the push-pull transistors to turn the third transistor on. The feedback loop optionally includes a delay circuit to prevent malfunctions caused by the differences in voltage associated with sensing the internal power supply voltage at remote locations on a memory device.