The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 2000
Filed:
Jun. 03, 1998
Chikayoshi Morishima, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A delay circuit (7) delays a transfer signal (V1) transferred through a transfer signal line (1) by the first delay time (dt1) to generate the first delayed signal (V9) and delays the first delayed signal (V9) by the second delay time (dt2) to generate the second delayed signal (V10). The second current mirror differential amplifier circuit (11) receives the transfer signal (1) and the second delayed signal (V10), whose ground terminal is connected to the first delayed signal line (9). On the other hand, the first current mirror differential amplifier circuit (14) also receives the transfer signal (V1) and the second delayed signal (V10), whose power-supply terminal is connected to the first delayed signal line (9). In response to a rise of the input signal (V1), the circuit (14) starts its operation to change a level of an output signal (V6) from 'L' level to 'H' level, remaining thereafter. After that, in response to a fall of the input signal (V1), the circuit (11) starts its operation to change the level of the output signal (V6) from 'H' level to 'L' level. With this configuration, a receiver circuit of a semiconductor circuit device achieves a faster operation and a lower power consumption.