Digital phase acquisition with delay locked loop

Abstract

A digital phase acquisition clock recovery circuit includes a digital phase-locked loop that employs a truth table decoder to set the actual delay through a plurality of individual delay elements to generate a plurality of clock phase signals approximately equally spaced in time over one reference clock cycle, and a data sampler circuit that generates a plurality of received data samples from an incoming data sample taken at the rising edge of the respective clock phase signals and synchronizes the data samples to reference clock on a bit period-by-bit period basis. A digital phase acquisition circuit includes an edge detector which evaluates the data samples over each bit period to detect the location of a transition between respective adjacent samples, wherein logic is employed to continually determine the 'relative quality' of each data sample, based upon its sampling time being furthest from a detected edge transition. The data sample phase associated with the highest relative quality value integrated over time is then used to recover the incoming (i.e., optimally phased) data signal.