Multiport memory having plurality of groups of bit lines

Abstract

Disclosed is a multiport memory capable of operating at a higher speed while minimizing the adverse effect of an adjoining bit line due to a parasitic capacitance. The multiport memory includes complementary write data lines and a read data line, wherein the read data line is sandwiched between the complementary write data lines. In a memory in which one port is a first port used exclusively for writing and the other port is a second port used exclusively for reading, and a group of bit lines includes complementary write data lines associated with the first port and a read data line associated with the second port, the complementary write data lines function as shield lines so as to minimize the adverse effect of noise upon the read data line. When the same column is accessed through the first port and second port, one of the potentials on the complementary write data lines is driven high and the other thereof is driven low. Adverse effects upon the read data line are therefore canceled out and thus minimized. In a memory having two groups of bit lines each including complementary write data lines and a read data line, the complementary write data lines belonging to each group are arranged to sandwich the read data line belonging to the same group. In this case, the write data lines and read data line belonging to the same group will not be used simultaneously. During reading, the potentials on the write data lines on both sides of the read data line are fixed to given values, and the write data lines on both sides of the read data line work as shield lines.